Present code division multiple access (CDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. These different data signals arrive at the receiver via multiple paths due to ground clutter and unpredictable signal reflection. Additive effects of these multiple data signals at the receiver may result in significant fading or variation in received signal strength. In general, this fading due to multiple data paths may be diminished by spreading the transmitted energy over a wide bandwidth. This wide bandwidth results in greatly reduced fading compared to narrow band transmission modes such as frequency division multiple access (FDMA) or time division multiple access (TDMA).
New standards are continually emerging for next generation wideband code division multiple access (WCDMA) communication systems as described in U.S. patent application Ser. No. 90/217,759, entitled Simplified Cell Search Scheme for First and Second Stage, filed Dec. 21, 1998, and incorporated herein by reference. These WCDMA systems are coherent communications systems with pilot symbol assisted channel estimation schemes. These pilot symbols are transmitted as quadrature phase shift keyed (QPSK) known data in predetermined time frames to any receivers within the cell or within range. The frames may propagate in a discontinuous transmission (DTX) mode within the cell. For voice traffic, transmission of user data occurs when the user speaks, but no data symbol transmission occurs when the user is silent. Similarly for packet data, the user data may be transmitted only when packets are ready to be sent. The frames include pilot symbols as well as other control symbols such as transmit power control (TPC) symbols and rate information (RI) symbols. These control symbols include multiple bits otherwise known as chips to distinguish them from data bits. The chip transmission time (TC), therefore, is equal to the symbol time rate (T) divided by the number of chips in the symbol (N). This number of chips in the symbol is the spreading factor.
A WCDMA base station must broadcast primary (PSC) and secondary (SSC) synchronization codes to properly establish communications with a mobile receiver. The PSC identifies the source as a base station within the cell. The SSC further identifies a group of synchronization codes that are selectively assigned to base stations that may transmit within the cell. Referring now to FIG. 1, there is a simplified block diagram of a circuit of the prior art for generating primary and secondary search codes. These search codes modulate or spread the transmitted signal so that a mobile receiver may identify it. Circuits 102 and 110 each produce a 256 cycle Hadamard sequence at leads 103 and 111, respectively. Either a true or a complement of a 16-cycle pseudorandom noise (PN) sequence, however, selectively modulates both sequences. This 16-cycle PN sequence is preferably a binary Lindner sequence given by Z={1,1,−1,−1,−1,−1, 1,−1,1,1,−1,1,1,1,−1,1}. Each element of the Lindner sequence is further designated z1–z16, respectively. Circuit 108 generates a 256-cycle code at lead 109 as a product of the Lindner sequence and each element of the sequence. The resulting PN sequence at lead 109, therefore, has the form {Z,Z,−Z,−Z,−Z,−Z,Z,−Z,Z,Z,−Z,Z,Z,Z,−Z,Z}. Exclusive-OR circuit 112 modulates the Hadamard sequence on lead 111 with the PN sequence on lead 109, thereby producing a PSC on lead 114. Likewise, exclusive-OR circuit 104 modulates the Hadamard sequence on lead 103 with the PN sequence on lead 109, thereby producing an SSC on lead 106.
A WCDMA mobile communication system must initially acquire a signal from a remote base station to establish communications within a cell. This initial acquisition, however, is complicated by the presence of multiple unrelated signals from the base station that are intended for other mobile systems within the cell as well as signals from other base stations. The base station continually transmits a special signal at 16 KSPS on a perch channel, much like a beacon, to facilitate this initial acquisition. The perch channel format includes a frame with sixteen time slots, each having a duration of 0.625 milliseconds. Each time slot includes four common pilot symbols, four transport channel data symbols and two search code symbols. These search code symbols include the PSC and SSC symbols transmitted in parallel. These search code symbols are not modulated by the long code, so a mobile receiver need not decode these signals with a Viterbi decoder to properly identify the base station. Proper identification of the PSC and SSC by the mobile receiver, therefore, limits the final search to one of sixteen groups of thirty-two comma free codes each that specifically identify a base station within the cell to a mobile unit.
Referring to FIG. 2, there is a circuit of the prior art for detecting the PSC and SSC generated by the circuit of FIG. 1. The circuit receives the PSC symbol from the transmitter as an input signal IN on lead 200. The signal is periodically sampled in response to a clock signal by serial register 221 at an oversampling rate n. Serial register 221, therefore, has 15*n stages for storing each successive sample of the input signal IN. Serial register 221 has 16 (N) taps 242–246 that produce 16 respective parallel tap signals. A logic circuit including 16 XOR circuits (230, 232, 234) receives the respective tap signals as well as 16 respective PN signals to produce 16 output signals (231, 233, 235). This PN sequence matches the transmitted sequence from circuit 108 and is preferably a Lindner sequence. Adder circuit 248 receives the 16 output signals and adds them to produce a sequence of output signals at terminal 250 corresponding to the oversampling rate n.
A 16-symbol accumulator circuit 290 receives the sequence of output signals on lead 250. The accumulator circuit 290 periodically samples the sequence on lead 250 in serial register 291 in response to the clock signal at the oversampling rate n. Serial register 291, therefore, has 240*n stages for storing each successive sample. Serial register 291 has 16 taps 250–284 that produce 16 respective parallel tap signals. Inverters 285 invert tap signals corresponding to negative elements of the Lindner sequence. Adder circuit 286 receives the 16 output signals and adds them to produce a match signal MAT at output terminal 288 in response to an appropriate PSC or SSC.
These circuits of the prior art require significant memory and processing power to generate and identify the PSC and SSC. Referring to FIG. 3, there is an improved circuit of the prior art that substantially reduces the required processing power of a mobile unit for generating a PN sequence for the reverse link. The circuit includes N stages for generating a length L=2N sequence. Each stage includes a respective delay circuit 302–306, an adder circuit 308–312, a subtracter circuit 314–318 and a multiplier circuit 320–324. Each delay circuit further includes a respective number of memory elements for storing the PN sequence in response to a clock signal. An exemplary length 256 circuit, therefore, includes eight delay circuits with corresponding delays D1–DN of 1, 2, 4, 8, 16, 32, 64 and 128, respectively. The circuit produces Golay complementary sequences Rra(k) and Rrb(k) in parallel at output terminals 326 and 328. The circuit requires 2log2(256) or 16 complex add operations for each sequence output sample. By way of comparison, this is approximately half the number of complex add operations required by the circuit of FIG. 2.
Several problems with the circuit of FIG. 3 render this solution less than ideal. The circuit still utilizes complex multiply operations. Furthermore, the circuit requires extensive memory to implement the delay circuits 302–306. For example, if input sequence r(k) is N bits wide, then each successive add operation increases the sequence width by one bit resulting in a sequence width of N+8 bits at output terminals 326 and 328. This increased width together with an increasing delay requires N+2(N+1)+4(N+2)+ . . . +128(N+7) or 255N+1538 delay memory elements. This requires extensive layout area and increases power consumption. Both considerations are especially disadvantageous for mobile communications systems.